Verilog syntax highlighting

[Eric Bouyoux]

Hi,

I would like that the following expressions to appear with a different
color in Verilog language.

#(IP_DATA_WIDTH/2)       
#(CORE_DATA_WIDTH)                   
#(.cellSize(IP_DATA_WIDTH), .testEnable_hold_11(0))   
#(.testEnable_hold_01(0))               
#12   
#(12)   

in the following lines :

D_TCD_tri    #(IP_DATA_WIDTH/2)I_D_TCD_tri_A                           
(.A(RA32_ramData)) ;
D_TCD_tri    #(CORE_DATA_WIDTH)                    I_D_TCD_tri_B       
(.A(memoryOut)) ;
D_TCD_tri    #(.cellSize(IP_DATA_WIDTH), .testEnable_hold_11(0))   
I_D_TCD_tri_C        (.A(IP_dataToRam)) ;
D_TCD_latpRnS    #(.testEnable_hold_01(0))               
I_D_TCD_latpRnS_D    (.D(IP_ramSelectP2)) ;

    #12    ebeb =
    #(12)    ebeb =

With the following regular expression,
 
((#\([^\)]+\))|(#\d+)|(#[^\s]*))

all expressions work except the 3rd one (#(.cellSize(IP_DATA_WIDTH),
.testEnable_hold_11(0))).

Could you help me to find the regular expression that will do the job.

Regards.

Eric.